About Me
I am currently a master’s student in the Department of Electrical Engineering at Columbia University, where I am supervised by Prof. Zishen Wan.
I received my bachelor’s degree in Electronic Engineering from the Hong Kong University of Science and Technology (HKUST), Hong Kong, China, in June 2026, under the supervision of Prof. Qiming Shao.
My research interests lie in energy-efficient, domain-specific edge chips for diverse workloads, including general-purpose AI models and optimization problems. I am particularly interested in cross-layer innovations that span algorithms, architectures, circuits, and device design.
Research Interests
- Energy-efficient accelerators for physical AI models, including vision-language-action (VLA) models and World Action Models (WAMs), through algorithm-architecture co-design.
- Efficient chips and architectures for general-purpose models, including large language models (LLMs), diffusion models, and convolutional neural networks (CNNs), through algorithm-architecture co-design.
- In-memory-computing architectures and device co-design for efficient combinatorial optimization solvers, especially probabilistic Ising machines.
Chip Gallery
News
- 09.2026: Very happy to join the Wan Lab to explore software-hardware co-design for efficient physical AI accelerators, including vision-language-action (VLA) models and World Action Models (WAMs).
- 05.2026: Honored to receive the Kerry Holdings UROP Scholarship at HKUST, earning Second Runner-Up and Best Poster distinctions (HK$7,500).
- 01.2026: Our INTERMAG paper, Three-body IM, has been accepted! Paper
- 08.2025: Our IEDM paper, Analog-IM, was accepted! Paper
- 06.2025: Excited to begin my summer research internship at the Duke Center for Electronics Innovation (DCEI), under the supervision of Prof. Yiran Chen.
- 09.2022: Honored to join the Hong Kong University of Science and Technology (HKUST) with a scholarship of HK$140,000 per semester to begin my bachelor’s degree.
Projects
Energy-efficient AI Accelerator Architecture for CNN and LLM Inference
C. Zhou, Y. Lu et al. (Co-author; submitted)
An accelerator architecture developed through algorithm-hardware co-design for efficient inference on CNNs and LLMs, covering the computation engine, RTL implementation, and integration into a RISC-V-based system. Further details will be released upon publication.
Three-body Probabilistic Ising Machine with In-memory Computing based on Dual-mode Spintronic Memristor
Y. Lu, G. Zeng et al. (First author; accepted)
A three-body probabilistic Ising machine with in-memory computing based on dual-mode spintronic memristors. The project explores hardware support for complex combinatorial optimization problems, including a three-body Hamiltonian computing unit.
Energy-efficient Probabilistic Ising Machine with Voltage-controlled MRAM and Reconfigurable Hamiltonian Computing Unit
Y. Hou, Y. Lu et al. (Co-author; in preparation)
An energy-efficient probabilistic Ising machine that uses VCMA-MTJ devices for probabilistic spin generation and a reconfigurable Hamiltonian computing unit for mixed-precision optimization workloads.
The associated 28 nm VCMA-MTJ P-bit chip provides 96 Kb capacity, 8-bit I/O, 5 ns read time, and 148 fJ/bit read energy.
Fully Analog In-Memory Annealing Ising Machine with Unified Deterministic and Probabilistic Computing Array Using CMOS-integrated VCMA-MTJ
Y. Hou, Z. Xiao, X. Wu, Z. Tong, S. Wang, M. Chen, C. Chan, Y. Lu et al. (Accepted)
An analog in-memory annealing Ising machine that integrates deterministic and probabilistic computing in a CMOS-integrated VCMA-MTJ array.
Engineering Skills
Digital and Simulator Design
- Performance evaluation of existing accelerators through C-based simulation, measuring computation, memory traffic, speedup, and energy against published baselines.
- RTL design of specialized functional units for SoC-based accelerators in Verilog, together with the surrounding compute and control logic.
- FPGA-level demonstration of designed accelerators, from synthesis and waveform bring-up to on-board functional validation.
Hardware Verification
- Functional verification of digital blocks with UVM and SystemVerilog, including testbench construction and coverage-driven simulation.
- Functional verification of digital blocks with JasperGold, using assertion- and property-based checks.
VLSI and Device Design
- Analog in-memory-computing circuit design built on emerging non-volatile memory devices.
- Compact modeling of emerging devices, capturing switching dynamics for circuit-level simulation.
Contact
The best place to find my latest public code and project work is GitHub.
I am gradually adding more project write-ups and technical notes to this site.