Projects
Energy-efficient AI Accelerator Architecture for CNN and LLM Inference
C. Zhou, Y. Lu et al. (Co-author; submitted)
An accelerator architecture developed through algorithm-hardware co-design for efficient inference on CNNs and LLMs, covering the computation engine, RTL implementation, and integration into a RISC-V-based system. Further details will be released upon publication.
Three-body Probabilistic Ising Machine with In-memory Computing based on Dual-mode Spintronic Memristor
Y. Lu, G. Zeng et al. (First author; accepted)
A three-body probabilistic Ising machine with in-memory computing based on dual-mode spintronic memristors. The project explores hardware support for complex combinatorial optimization problems, including a three-body Hamiltonian computing unit.
Energy-efficient Probabilistic Ising Machine with Voltage-controlled MRAM and Reconfigurable Hamiltonian Computing Unit
Y. Hou, Y. Lu et al. (Co-author; in preparation)
An energy-efficient probabilistic Ising machine that uses VCMA-MTJ devices for probabilistic spin generation and a reconfigurable Hamiltonian computing unit for mixed-precision optimization workloads.
The associated 28 nm VCMA-MTJ P-bit chip provides 96 Kb capacity, 8-bit I/O, 5 ns read time, and 148 fJ/bit read energy.
Fully Analog In-Memory Annealing Ising Machine with Unified Deterministic and Probabilistic Computing Array Using CMOS-integrated VCMA-MTJ
Y. Hou, Z. Xiao, X. Wu, Z. Tong, S. Wang, M. Chen, C. Chan, Y. Lu et al. (Accepted)
An analog in-memory annealing Ising machine that integrates deterministic and probabilistic computing in a CMOS-integrated VCMA-MTJ array.